4.6.4.1 Logic gates
Logic Gates are electrical components that are the foundation of all of computing. Computers rely on logic gates made out of transistors to perform actions. These logic gates are based off of boolean algebra, where the only values can be either a 1
or a 0
, representing an on
or off
state.
Because the boolean number system has only two digits for counting, conversion is required when converting numbers to and from decimal, our system of counting.
NOT Gate
A NOT
gate toggles the state of the input.
If the input is off, the output is on.
If the input is on, the output is off.
Diagram 
Boolean Algebra 

\(\overline A\) 
Truth Table
AND Gate
An AND
gate checks if both inputs are on.
If both inputs are both on, the output will be on.
Diagram 
Boolean Algebra 

\(A . B = Q\) 
Truth Table
A 
B 
Q 
0 
0 
0 
0 
1 
0 
1 
0 
0 
1 
1 
1 
OR Gate
An OR
gate turns on when any input is on.
When one or more inputs are on, the output will be on.
Diagram 
Boolean Algebra 

\(A + B = Q\) 
Truth Table
A 
B 
Q 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
1 
XOR Gate
Diagram 
Boolean Algebra 

\(A \oplus B = Q\) 
Truth Table
A 
B 
Q 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
0 
NAND Gate
Diagram 
Boolean Algebra 

\(\overline{A \cap B} = Q\) 
Truth Table
A 
B 
Q 
0 
0 
1 
0 
1 
1 
1 
0 
1 
1 
1 
0 
NOR Gate
Diagram 
Boolean Algebra 

\(\overline{A \cup B} = Q\) 
Truth Table
A 
B 
Q 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
0 
Half Adder
The half adder adds two single binary digits A and B, and outputs the sum and a carry bit.
The carry bit is used to pass the overflow onto the next digit.
Diagram 
Boolean Algebra 

\(A \cap B = C\) \(A \oplus B = S\) 
Truth Table
A 
B 
\(C_{out}\) 
S (Sum) 
0 
0 
0 
0 
0 
1 
0 
1 
1 
0 
0 
1 
1 
1 
1 
0 
Full Adder
A full adder adds two single binary digits A and B, as well as accounts for bits carried in.
Diagram 
Boolean Algebra 

\(A \cap B = C\) \(A \oplus B = S\) 
Truth Table
A 
B 
\(C_{in}\) 
\(C_{out}\) 
S 
0 
0 
0 
0 
0 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
0 
1 
1 
1 
0 
1 
0 
0 
0 
1 
1 
0 
1 
1 
0 
1 
1 
0 
1 
0 
1 
1 
1 
1 
1 